PIC16C55X(A)
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
theTRISB register puts the corresponding output driver
in a high impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Note: If a change on the I/O pin should occur when the
read operation is being executed (start of the Q2
cycle), then the RBIF interrupt flag may not
get set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 5-4: BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
weak
FIGURE 5-3: BLOCK DIAGRAM OF
P
pull-up
RB7:RB4 PINS
Data Latch
Data bus
D
Q
VDD
RBPU(2)
I/O
pin(1)
weak
WR PortB
P
CK
CK
pull-up
Data Latch
Data bus
D
Q
D
Q
TTL
Input
Buffer
I/O
pin(1)
WR PortB
WR TRISB
CK
TRIS Latch
D
Q
WR TRISB
TTL
Input
Buffer
RD TRISB
RD PortB
CK
Q
D
ST
Buffer
EN
RD TRISB
RD PortB
Latch
D
Q
Q
RB0/INT
ST
Buffer
EN
RD Port
Set RBIF
From other
RB7:RB4 pins
D
Note 1: I/O pins have diode protection to VDD and VSS.
EN
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
RD Port
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
1997 Microchip Technology Inc.
Preliminary
DS40143B-page 25
MICROCHIP [ MICROCHIP ]
