PIC16C55X(A)
FIGURE 5-2: BLOCK DIAGRAM OF RA4 PIN
5.0
I/O PORTS
The PIC16C55X(A) have two ports, PORTA and PORTB.
Data
bus
5.1
PORTA and TRISA Registers
D
Q
Q
WR
PORTA is a 5-bit wide latch. RA4 is a SchmittTrigger input
and an open drain output.Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers) which can config-
ure these pins as input or output.
PORTA
CK
I/O pin(1)
N
Data Latch
D
Q
VSS
WR
TRISA
Schmitt
Trigger
input
Q
CK
A '1' in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A '0' in the TRISA register
puts the contents of the output latch on the selected pin(s).
TRISA Latch
buffer
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
RD TRISA
Q
D
EN
EN
RD PORTA
Note: On reset, the TRISA register is set to all inputs.
FIGURE 5-1: BLOCK DIAGRAM OF
PORT PINS RA<3:0>
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
Data
bus
D
Q
Q
VDD
P
WR
PortA
CK
Data Latch
N
Q
D
I/O pin
WR
TRISA
VSS
Q
CK
Schmitt
Trigger
input
TRIS Latch
buffer
RD TRISA
Q
D
EN
RD PORTA
1997 Microchip Technology Inc.
Preliminary
DS40143B-page 23
MICROCHIP [ MICROCHIP ]
