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PIC16F73-I/SPG 参数 Datasheet PDF下载

PIC16F73-I/SPG图片预览
型号: PIC16F73-I/SPG
PDF下载: 下载PDF文件 查看货源
内容描述: [28 Pin, 7KB Std Flash, 192 RAM, 22 I/O, -40C to +85C, 28-SPDIP, TUBE]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F73-I/SPG的Datasheet PDF文件第86页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第87页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第88页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第89页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第91页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第92页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第93页浏览型号PIC16F73-I/SPG的Datasheet PDF文件第94页  
PIC16F7X  
with minimal software overhead (moving the ADRES to  
the desired location). The appropriate analog input  
channel must be selected and an appropriate acquisi-  
tion time should pass before the special event trigger”  
sets the GO/DONE bit (starts a conversion).  
11.7 Use of the CCP Trigger  
An A/D conversion can be started by the special event  
triggerof the CCP2 module. This requires that the  
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-  
grammed as 1011and that the A/D module is enabled  
(ADON bit is set). When the trigger occurs, the  
GO/DONE bit will be set, starting the A/D conversion,  
and the Timer1 counter will be reset to zero. Timer1 is  
reset to automatically repeat the A/D acquisition period  
If the A/D module is not enabled (ADON is cleared),  
then the special event triggerwill be ignored by the  
A/D module, but will still reset the Timer1 counter.  
TABLE 11-2: SUMMARY OF A/D REGISTERS  
Value on:  
POR,  
BOR  
Value on  
all other  
RESETS  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0Bh,8Bh,  
INTCON  
GIE  
PEIE TMR0IE  
INTE  
RBIE  
TMR0IF  
INTF  
RBIF 0000 000x 0000 000u  
10Bh, 18Bh  
(1)  
0Ch  
0Dh  
PIR1  
PIR2  
PSPIF  
ADIF  
RCIF  
TXIF  
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000  
CCP2IF ---- ---0 ---- ---0  
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000  
(1)  
8Ch  
8Dh  
1Eh  
PIE1  
PSPIE  
ADIE  
RCIE  
TXIE  
PIE2  
CCP2IE ---- ---0 ---- ---0  
ADRES  
A/D Result Register  
xxxx xxxx uuuu uuuu  
1Fh  
9Fh  
05h  
85h  
ADCON0 ADCS1 ADCS0 CHS2  
CHS1  
CHS0 GO/DONE  
ADON 0000 00-0 0000 00-0  
ADCON1  
PORTA  
TRISA  
PCFG2  
RA2  
PCFG1 PCFG0 ---- -000 ---- -000  
RA5  
RA4  
RA3  
RA1  
RA0  
RE0  
--0x 0000 --0u 0000  
--11 1111 --11 1111  
PORTA Data Direction Register  
(2)  
09h  
89h  
PORTE  
RE2  
RE1  
---- -xxx ---- -uuu  
0000 -111 0000 -111  
(2)  
TRISE  
IBF  
OBF  
IBOV PSPMODE  
PORTE Data Direction Bits  
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.  
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.  
2: These registers are reserved on the PIC16F73/76.  
DS30325B-page 88  
2002 Microchip Technology Inc.  
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