PIC16F7X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Follow these steps when setting up a Synchronous
Slave Transmission:
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
1. Enable the synchronous slave serial port by set-
mode, in that the shift clock is supplied externally at the
ting bits SYNC and SPEN and clearing bit
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
a) The first word will immediately transfer to the
TSR register and transmit when the master
device drives the CK line.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
DS30325B-page 80
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
