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PIC16F73-I/SPG 参数 Datasheet PDF下载

PIC16F73-I/SPG图片预览
型号: PIC16F73-I/SPG
PDF下载: 下载PDF文件 查看货源
内容描述: [28 Pin, 7KB Std Flash, 192 RAM, 22 I/O, -40C to +85C, 28-SPDIP, TUBE]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X  
8.2  
CCP2 Module  
8.0  
CAPTURE/COMPARE/PWM  
MODULES  
Capture/Compare/PWM Register1 (CCPR1) is com-  
prised of two 8-bit registers: CCPR1L (low byte) and  
CCPR1H (high byte). The CCP2CON register controls  
the operation of CCP2. The special event trigger is  
generated by a compare match; it will clear both  
TMR1H and TMR1L registers, and start an A/D conver-  
sion (if the A/D module is enabled).  
Each Capture/Compare/PWM (CCP) module contains  
a 16-bit register which can operate as a:  
16-bit Capture register  
16-bit Compare register  
PWM Master/Slave Duty Cycle register  
Additional information on CCP modules is available in  
the PICmicroMid-Range MCU Family Reference  
Manual (DS33023) and in Application Note AN594,  
Using the CCP Modules(DS00594).  
Both the CCP1 and CCP2 modules are identical in  
operation, with the exception being the operation of the  
special event trigger. Table 8-1 and Table 8-2 show the  
resources and interactions of the CCP module(s). In  
the following sections, the operation of a CCP module  
is described with respect to CCP1. CCP2 operates the  
same as CCP1, except where noted.  
TABLE 8-1:  
CCP MODE - TIMER  
RESOURCES REQUIRED  
8.1  
CCP1 Module  
CCP Mode  
Capture  
Compare  
PWM  
Timer Resource  
Capture/Compare/PWM Register1 (CCPR1) is com-  
prised of two 8-bit registers: CCPR1L (low byte) and  
CCPR1H (high byte). The CCP1CON register controls  
the operation of CCP1. The special event trigger is  
generated by a compare match and will clear both  
TMR1H and TMR1L registers.  
Timer1  
Timer1  
Timer2  
TABLE 8-2:  
INTERACTION OF TWO CCP MODULES  
CCPx Mode CCPy Mode  
Interaction  
Capture  
Capture  
Capture  
Same TMR1 time-base.  
Same TMR1 time-base.  
Same TMR1 time-base.  
Compare  
Compare  
PWM  
Compare  
PWM  
The PWMs will have the same frequency and update rate (TMR2 interrupt).  
The rising edges are aligned.  
PWM  
PWM  
Capture  
None.  
None.  
Compare  
2002 Microchip Technology Inc.  
DS30325B-page 53