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PIC16C715-04E/SS 参数 Datasheet PDF下载

PIC16C715-04E/SS图片预览
型号: PIC16C715-04E/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器与A / D转换器 [8-Bit CMOS Microcontrollers with A/D Converter]
分类和应用: 转换器微控制器
文件页数/大小: 176 页 / 1596 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C71X  
4.3.2  
STACK  
4.3  
PCL and PCLATH  
The program counter (PC) is 13-bits wide.The low byte  
comes from the PCL register, which is a readable and  
writable register. The upper bits (PC<12:8>) are not  
readable, but are indirectly writable through the  
PCLATH register. On any reset, the upper bits of the  
PC will be cleared. Figure 4-14 shows the two situa-  
tions for the loading of the PC. The upper example in  
the figure shows how the PC is loaded on a write to  
PCL (PCLATH<4:0> PCH).The lower example in the  
figure shows how the PC is loaded during a CALL or  
GOTOinstruction (PCLATH<4:3> PCH).  
The PIC16CXX family has an 8 level deep x 13-bit wide  
hardware stack. The stack space is not part of either  
program or data space and the stack pointer is not  
readable or writable.The PC is PUSHed onto the stack  
when a CALL instruction is executed or an interrupt  
causes a branch. The stack is POPed in the event of a  
RETURN, RETLW or a RETFIE instruction execution.  
PCLATH is not affected by a PUSH or POP operation.  
The stack operates as a circular buffer.This means that  
after the stack has been PUSHed eight times, the ninth  
push overwrites the value that was stored from the first  
push. The tenth push overwrites the second push (and  
so on).  
FIGURE 4-14: LOADING OF PC IN  
DIFFERENT SITUATIONS  
Note 1: There are no status bits to indicate stack  
PCH  
PCL  
overflow or stack underflow conditions.  
12  
8
7
0
Instruction with  
PCL as  
Destination  
Note 2: There are no instructions/mnemonics  
called PUSH or POP. These are actions  
that occur from the execution of the CALL,  
RETURN, RETLW, and RETFIE instruc-  
tions, or the vectoring to an interrupt  
address.  
PC  
8
PCLATH<4:0>  
PCLATH  
5
ALU  
PCH  
12 11 10  
PCL  
4.4  
Program Memory Paging  
8
7
0
The PIC16C71X devices ignore both paging bits  
(PCLATH<4:3>, which are used to access program  
memory when more than one page is available. The  
use of PCLATH<4:3> as general purpose read/write  
bits for the PIC16C71X is not recommended since this  
may affect upward compatibility with future products.  
GOTO, CALL  
PC  
PCLATH<4:3>  
PCLATH  
11  
2
Opcode <10:0>  
4.3.1  
COMPUTED GOTO  
A computed GOTO is accomplished by adding an off-  
set to the program counter (ADDWF PCL).When doing a  
table read using a computed GOTO method, care  
should be exercised if the table location crosses a PCL  
memory boundary (each 256 byte block). Refer to the  
application note “Implementing a Table Read" (AN556).  
1997 Microchip Technology Inc.  
DS30272A-page 23  
 
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