PIC16C71X
FIGURE 5-1: BLOCK DIAGRAM OF
5.0
I/O PORTS
RA3:RA0 PINS
Applicable Devices 710 71 711 715
Data
bus
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
D
Q
Q
VDD
P
WR
Port
CK
5.1
PORTA and TRISA Registers
Data Latch
PORTA is a 5-bit latch.
I/O pin(1)
N
D
Q
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers) which can configure
these pins as output or input.
WR
TRIS
VSS
Analog
Q
CK
input
mode
TRIS Latch
Setting aTRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
TTL
input
buffer
RD TRIS
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Q
D
EN
RD PORT
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
To A/D Converter
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 5-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
bus
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
D
Q
Q
WR
PORT
CK
I/O pin(1)
N
Data Latch
EXAMPLE 5-1: INITIALIZING PORTA
D
Q
VSS
BCF
CLRF
STATUS, RP0
PORTA
;
WR
TRIS
; Initialize PORTA by
; clearing output
; data latches
Schmitt
Trigger
input
Q
CK
TRIS Latch
buffer
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
RD TRIS
MOVWF TRISA
; Set RA<3:0> as inputs
; RA<4> as outputs
; TRISA<7:5> are always
; read as '0'.
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1997 Microchip Technology Inc.
DS30272A-page 25
MICROCHIP [ MICROCHIP ]
