PIC16C63A/65B/73B/74B
TABLE 11-6:
Address
0Bh,8Bh
0Ch
18h
1Ah
8Ch
98h
99h
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
GIE
SPEN
PSPIE
(1)
Name
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Bit 6
PEIE
RX9
ADIE
(2)
Bit 5
T0IE
RCIF
SREN
RCIE
TXEN
Bit 4
INTE
TXIF
CREN
TXIE
SYNC
Bit 3
RBIE
SSPIF
—
SSPIE
—
Bit 2
T0IF
CCP1IF
FERR
CCP1IE
BRGH
Bit 1
INTF
TMR2IF
OERR
TMR2IE
TRMT
Bit 0
RBIF
RX9D
Value on:
POR,
BOR
0000 000x
Value on
all other
RESETS
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
PSPIF
(1)
ADIF
(2)
TMR1IF
0000 0000
0000 -00x
0000 0000
USART Receive register
CSRC
TX9
TX9D
TMR1IE
0000 0000
0000 -010
0000 0000
Baud Rate Generator register
Legend:
u
= unchanged,
x
= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous master reception.
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2:
Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
RCIF bit
(interrupt)
Read
RXREG
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Note:
Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
2000 Microchip Technology Inc.
DS30605C-page 75
MICROCHIP [ MICROCHIP TECHNOLOGY ]
