PIC16F684
• FOSC/16
9.1.4
CONVERSION CLOCK
• FOSC/32
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ADCON1<6:4>). There are seven possible
clock options:
• FOSC/64
• FRC (dedicated internal oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 µs. Table 9-1 shows a few TAD calculations for
selected frequencies.
• FOSC/2
• FOSC/4
• FOSC/8
TABLE 9-1:
TAD VS. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)
Device Frequency
Operation
2 TOSC
ADCS2:ADCS0
20 MHz
100 ns(2)
200 ns(2)
400 ns(2)
800 ns(2)
1.6 µs
5 MHz
400 ns(2)
800 ns(2)
1.6 µs
4 MHz
500 ns(2)
1.0 µs(2)
2.0 µs
1.25 MHz
1.6 µs
000
100
001
101
010
110
x11
4 TOSC
3.2 µs
8 TOSC
6.4 µs
16 TOSC
32 TOSC
64 TOSC
A/D RC
3.2 µs
4.0 µs
12.8 µs(3)
25.6 µs(3)
51.2 µs(3)
2-6 µs(1,4)
6.4 µs
8.0 µs(3)
16.0 µs(3)
2-6 µs(1,4)
3.2 µs
2-6 µs(1,4)
12.8 µs(3)
2-6 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
9.1.5
STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
FIGURE 9-2:
A/D CONVERSION TAD CYCLES
TCY to TAD
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
TAD
7
TAD
8
TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO bit
ADRESH and ADRESL registers are Loaded,
GO bit is Cleared,
ADIF bit is Set,
Holding Capacitor is Connected to Analog Input
DS41202C-page 64
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
