PIC16F684
4.2.4.3
RA2/AN2/T0CKI/INT/C1OUT
4.2.4.4
RA3/MCLR/VPP
Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
Figure 4-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose input
• an analog input for the A/D
• the clock input for TMR0
• as Master Clear Reset with weak pull-up
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
• an external edge triggered interrupt
• a digital output from comparator 1
VDD
MCLRE
Weak
FIGURE 4-3:
BLOCK DIAGRAM OF RA2
Analog(1)
Input Mode
Data Bus
MCLRE
Data Bus
D
Reset
Input
pin
Q
Q
VDD
RD
TRISA
WR
CK
WPUA
VSS
Weak
MCLRE
VSS
RD
RAPU
RD
WPUA
PORTA
D
Q
Q
COUT 1
Enable
VDD
Q
Q
D
CK
WR
IOCA
D
Q
Q
Q3
EN
WR
CK
RD
IOCA
COUT
1
0
PORTA
D
I/O PIN
EN
D
Q
Q
Interrupt-on-
Change
WR
CK
VSS
TRISA
RD PORTA
Analog(1)
Input Mode
RD
TRISA
RD
PORTA
D
Q
Q
Q
Q
D
CK
WR
IOCA
Q3
EN
RD
IOCA
D
EN
Interrupt-on-
Change
RD PORTA
To TMR0
To INT
To A/D Converter
Note 1: Analog Input mode is generated by ANSEL.
2004 Microchip Technology Inc.
Preliminary
DS41202C-page 37
MICROCHIP [ MICROCHIP ]
