PIC16F684
TABLE 2-2:
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
—
TRISC
—
—
PCLATH
INTCON
PIE1
—
PCON
OSCCON
OSCTUNE
ANSEL
PR2
—
—
WPUA
(3)
IOCA
—
—
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
(1)
PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
Name
xxxx xxxx
1111 1111
0000 0000
—
—
—
—
—
—
—
—
INTEDG
(1)
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
Indirect Data Memory Address Pointer
—
Unimplemented
—
Unimplemented
Unimplemented
—
GIE
EEIE
—
PEIE
ADIE
—
T0IE
CCP1IE
Write Buffer for upper 5 bits of Program Counter
INTE
C2IE
RAIE
C1IE
T0IF
OSFIE
INTF
TMR2IE
RAIF
TMR1IE
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
—
--11 1111
—
—
---0 0000
0000 0000
0000 0000
—
Unimplemented
—
—
—
ANS7
—
IRCF2
—
ANS6
ULPWUE
IRCF1
—
ANS5
SBODEN
IRCF0
TUN4
ANS4
—
OSTS
(2)
—
HTS
TUN2
ANS2
POR
LTS
TUN1
ANS1
BOD
SCS
TUN0
ANS0
--01 --qq
-110 x000
---0 0000
1111 1111
1111 1111
—
—
TUN3
ANS3
Timer2 Module Period Register
Unimplemented
Unimplemented
—
—
Unimplemented
Unimplemented
VREN
EEDAT7
EEADR7
—
—
EEDAT6
EEADR6
—
VRR
EEDAT5
EEADR5
—
—
EEDAT4
EEADR4
—
VR3
EEDAT3
EEADR3
WRERR
VR2
EEDAT2
EEADR2
WREN
VR1
EEDAT1
EEADR1
WR
VR0
EEDAT0
EEADR0
RD
—
—
WPUA5
IOCA5
WPUA4
IOCA4
—
IOCA3
WPUA2
IOCA2
WPUA1
IOCA1
WPUA0
IOCA0
--11 -111
--00 0000
—
—
0-0- 0000
0000 0000
0000 0000
---- x000
---- ----
xxxx xxxx
EEPROM Control Register 2 (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
—
ADCS2
ADCS1
ADCS0
—
—
—
—
-000 ----
Legend:
Note 1:
2:
3:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
OSTS bit OSCCON <3> reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator.
RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
DS41202C-page 10
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
