PIC16F872
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB<7:4> pins changed state (must be cleared in software)
0= None of the RB<7:4> pins have changed state
DS30221A-page 14
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
