欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F876-20I/SO 参数 Datasheet PDF下载

PIC16F876-20I/SO图片预览
型号: PIC16F876-20I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS闪存微控制器 [28/40-pin 8-Bit CMOS FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 200 页 / 3544 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F876-20I/SO的Datasheet PDF文件第131页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第132页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第133页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第134页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第136页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第137页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第138页浏览型号PIC16F876-20I/SO的Datasheet PDF文件第139页  
PIC16F87X  
FIGURE 12-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
(2)  
TOST  
CLKOUT(4)  
INT pin  
INTF flag  
Interrupt Latency  
(Note 2)  
(INTCON<1>)  
GIE bit  
Processor in  
SLEEP  
(INTCON<7>)  
INSTRUCTION FLOW  
PC  
PC  
PC+1  
PC+2  
PC+2  
PC + 2  
0004h  
0005h  
Instruction  
Inst(0004h)  
Inst(PC + 1)  
Inst(PC + 2)  
Inst(0005h)  
Inst(PC) = SLEEP  
fetched  
Instruction  
executed  
Dummy cycle  
Dummy cycle  
SLEEP  
Inst(PC + 1)  
Inst(PC - 1)  
Inst(0004h)  
Note 1: XT, HS or LP oscillator mode assumed.  
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.  
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.  
If GIE = ’0’, execution will continue in-line.  
4: CLKOUT is not available in these osc modes, but shown here for timing reference.  
12.14 In-Circuit Debugger  
12.16 ID Locations  
When the DEBUG bit in the configuration word is pro-  
grammed to a ’0’, the In-Circuit Debugger functionality  
is enabled. This function allows simple debugging func-  
tions when used with MPLAB. When the microcontrol-  
ler has this feature enabled, some of the resources are  
not available for general use. Table 12-7 shows which  
features are consumed by the background debugger.  
Four memory locations (2000h - 2003h) are designated  
as ID locations where the user can store checksum or  
other code-identification numbers. These locations are  
not accessible during normal execution but are read-  
able and writable during program/verify. It is recom-  
mended that only the 4 least significant bits of the ID  
location are used.  
TABLE 12-7: DEBUGGER RESOURCES  
I/O pins  
RB6, RB7  
Stack  
1 level  
Program Memory  
Address 0000h must be NOP  
Last 100h words  
Data Memory  
0x070(0x0F0, 0x170, 0x1F0)  
0x1EB - 0x1EF  
To use the In-Circuit Debugger function of the micro-  
controller, the design must implement In-Circuit Serial  
Programming connections to MCLR/VPP, VDD, GND,  
RB7 and RB6. This will interface to the In-Circuit  
Debugger module available from Microchip or one of  
the third party development tool companies.  
12.15 Program Verification/Code Protection  
If the code protection bit(s) have not been pro-  
grammed, the on-chip program memory can be read  
out for verification purposes.  
1999 Microchip Technology Inc.  
DS30292B-page 135