PIC16F87X
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1) ADIE
R/W-0
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
1999 Microchip Technology Inc.
DS30292B-page 21
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