PIC16F872
9.2.13 ACKNOWLEDGE SEQUENCE TIMING
the baud rate generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the baud rate generator is turned off,
and the SSP module then goes into IDLE mode.
(Figure 9-16)
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
9.2.13.13 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledege
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: TBRG = one baud rate generator period.
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 75
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