PIC16F872
9.2.3
SLEEP OPERATION
9.2.4
EFFECTS OF A RESET
While in SLEEP mode, the I2C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
A RESET disables the SSP module and terminates the
current transfer.
TABLE 9-3
REGISTERS ASSOCIATED WITH I2C OPERATION
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
PIR1
(1)
(1)
—
ADIF
ADIE
(1)
(1)
(1)
—
(1)
(1)
SSPIF
SSPIE
BCLIF
BCLIE
CCP1IF TMR2IF TMR1IF r0rr 0000 r0rr 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 r0rr 0000
PIE1
PIR2
EEIF
EEIE
—
—
—
—
(1)
(1)
-r-0 0--r -r-0 0--r
-r-0 0--r -r-0 0--r
xxxx xxxx uuuu uuuu
PIE2
—
(1)
—
SSPBUF
SSPCON
SSPCON2
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GCEN
SMP
SSPOV
ACKSTAT
CKE
SSPEN
ACKDT
D/A
CKP
ACKEN
P
SSPM3 SSPM2
SSPM1
RSEN
UA
SSPM0 0000 0000 0000 0000
RCEN
S
PEN
R/W
SEN
BF
0000 0000 0000 0000
0000 0000 0000 0000
2
Legend: x= unknown, u= unchanged, r= reserved, -= unimplemented read as ’0’. Shaded cells are not used by the SSP in I C
mode.
Note 1: These bits are reserved; always maintain these bits clear.
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 65
MICROCHIP [ MICROCHIP ]
