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PIC16F872-I/SS 参数 Datasheet PDF下载

PIC16F872-I/SS图片预览
型号: PIC16F872-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28引脚, 8位CMOS闪存微控制器 [28-Pin, 8-Bit CMOS FLASH Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 160 页 / 2454 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F872  
11.10.1 INT INTERRUPT  
11.11 Context Saving During Interrupts  
External interrupt on the RB0/INT pin is edge triggered,  
either rising, if bit INTEDG (OPTION_REG<6>) is set,  
or falling, if the INTEDG bit is clear. When a valid edge  
appears on the RB0/INT pin, flag bit INTF  
(INTCON<1>) is set. This interrupt can be disabled by  
clearing enable bit INTE (INTCON<4>). Flag bit INTF  
must be cleared in software in the interrupt service rou-  
tine before re-enabling this interrupt. The INT interrupt  
can wake-up the processor from SLEEP, if bit INTE was  
set prior to going into SLEEP. The status of global inter-  
rupt enable bit GIE decides whether or not the proces-  
sor branches to the interrupt vector following wake-up.  
See Section 11.13 for details on SLEEP mode.  
During an interrupt, only the return PC value is saved  
on the stack. Typically, users may wish to save key reg-  
isters during an interrupt (i.e., W register and STATUS  
register). This will have to be implemented in software.  
Since the upper 16 bytes of each bank are common in  
the PIC16F872 devices, temporary holding registers  
W_TEMP, STATUS_TEMP and PCLATH_TEMP  
should be placed in here. These 16 locations don’t  
require banking and therefore, make it easier for con-  
text save and restore. Example 11-1 can be used to  
save and restore context for interrupts.  
11.10.2 TMR0 INTERRUPT  
An overflow (FFh 00h) in the TMR0 register will set  
flag bit T0IF (INTCON<2>). The interrupt can be  
enabled/disabled by setting/clearing enable bit T0IE  
(INTCON<5>) (Section 5.0).  
11.10.3 PORTB INTCON CHANGE  
An input change on PORTB<7:4> sets flag bit RBIF  
(INTCON<0>). The interrupt can be enabled/disabled  
by setting/clearing enable bit RBIE (INTCON<4>)  
(Section 3.2).  
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM  
MOVWF  
SWAPF  
CLRF  
MOVWF  
MOVF  
MOVWF  
CLRF  
:
W_TEMP  
STATUS,W  
STATUS  
STATUS_TEMP  
PCLATH, W  
PCLATH_TEMP  
PCLATH  
;Copy W to TEMP register  
;Swap status to be saved into W  
;bank 0, regardless of current bank, Clears IRP,RP1,RP0  
;Save status to bank zero STATUS_TEMP register  
;Only required if using pages 1, 2 and/or 3  
;Save PCLATH into W  
;Page zero, regardless of current page  
:(ISR)  
:
MOVF  
MOVWF  
SWAPF  
PCLATH_TEMP, W  
PCLATH  
STATUS_TEMP,W  
;Restore PCLATH  
;Move W into PCLATH  
;Swap STATUS_TEMP register into W  
;(sets bank to original state)  
;Move W into STATUS register  
;Swap W_TEMP  
MOVWF  
SWAPF  
SWAPF  
STATUS  
W_TEMP,F  
W_TEMP,W  
;Swap W_TEMP into W  
DS30221A-page 106  
Preliminary  
1999 Microchip Technology Inc.  
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