PIC16F8X
TABLE 4-1
REGISTER FILE SUMMARY
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Address Name
Bank 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
01h
02h
INDF
TMR0
PCL
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
---- ----
xxxx xxxx
0000 0000
---- ----
uuuu uuuu
0000 0000
Low order 8 bits of the Program Counter (PC)
(2)
TO
Indirect data memory address pointer 0
03h
04h
05h
06h
07h
08h
09h
STATUS
FSR
IRP
RP1
RP0
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x xxxx
000q quuu
uuuu uuuu
---u uuuu
uuuu uuuu
---- ----
uuuu uuuu
uuuu uuuu
PORTA
PORTB
—
—
—
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB7
RB6
RB5
RB0/INT xxxx xxxx
---- ----
Unimplemented location, read as '0'
EEPROM data register
EEDATA
EEADR
xxxx xxxx
EEPROM address register
xxxx xxxx
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF
---0 0000
---0 0000
0000 000u
GIE
EEIE
T0IE
INTF
RBIF
0000 000x
Bank 1
80h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
1111 1111
---- ----
1111 1111
OPTION_
REG
81h
82h
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
PCL
Low order 8 bits of Program Counter (PC)
IRP RP1 RP0 TO
Indirect data memory address pointer 0
PORTA data direction register
0000 0000
0000 0000
(2)
83h
84h
85h
86h
STATUS
FSR
PD
Z
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---- ----
000q quuu
uuuu uuuu
---1 1111
1111 1111
---- ----
TRISA
TRISB
—
—
—
PORTB data direction register
Unimplemented location, read as '0'
87h
88h
EECON1
EECON2
—
—
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---- ----
---0 q000
---- ----
89h
EEPROM control register 2 (not a physical register)
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF
---0 0000
0000 000x
---0 0000
0000 000u
GIE
EEIE
T0IE
INTF
RBIF
Legend: x= unknown, u= unchanged. -= unimplemented read as '0', q= value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never trans-
ferred to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
