PIC16C5X
4.5.1
PAGING CONSIDERATIONS –
PIC16C56s/CR56s, PIC16C57s/CR57sAND
PIC16C58s/CR58s
FIGURE 4-12: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C57s/PIC16CR57s, AND
PIC16C58s/PIC16CR58s
If the Program Counter is pointing to the last address
of a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS
register will not be updated. Therefore, the next GOTO,
CALL, or Modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0
or PA1:PA0).
GOTO Instruction
10
9
8
7
0
PC
PCL
Instruction Word
2
PA1:PA0
7
0
For example, a NOP at location 1FFh (page 0)
increments the PC to 200h (page 1). A GOTO xxxat
200h will return the program to address 0xxh on page
0 (assuming that PA1:PA0 are clear).
STATUS
To prevent this, the page preselect bits must be
updated under program control.
CALL or Modify PCL Instruction
10
9
8
7
0
PC
PCL
4.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the reset vector.
Instruction Word
Reset to ‘0’
PA1:PA0
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is
pre-selected.
2
7
0
STATUS
Therefore, upon a RESET, a GOTOinstruction at the
reset vector location will automatically cause the
program to jump to page 0.
4.6
Stack
PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,
two-level hardware push/pop stack (Figure 4-2,
Figure 4-1, and Figure 4-3 respectively).
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLWinstruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
For the RETLWinstruction, the PC is loaded with the
Top Of Stack (TOS) contents. All of the devices
covered in this data sheet have a two-level stack. The
stack has the same bit width as the device PC.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 23
MICROCHIP [ MICROCHIP ]
