PIC16F627A/628A/648A
FIGURE 3-1:
BLOCK DIAGRAM
13
8
Data Bus
Program Counter
FLASH
Program
Memory
RAM
8-Level Stack
(13-bit)
File
Registers
Program
Bus
14
PORTA
RAM Addr (1)
9
Addr MUX
RA0/AN0
Instruction reg
RA1/AN1
Indirect
Addr
7
Direct Addr
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
8
FSR reg
STATUS reg
8
3
PORTB
MUX
Power-up
Timer
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
RB4/PGM
RB5
8
Timing
Generation
Watchdog
Timer
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Detect
Low-Voltage
Programming
MCLR VDD, VSS
Timer0
Timer1
Timer2
Comparator
CCP1
USART
Data EEPROM
VREF
Note: Higher order bits are from the STATUS register.
DS40044A-page 10
Preliminary
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
