PIC16F62X
9.4
Comparator Response Time
9.5
Comparator Outputs
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is guaranteed to have a valid level.
If the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise the
maximum delay of the comparators should be used
(Table 12-2 ).
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110 or 001, multiplexors
in the output path of the RA3 and RA4/T0CK1 pins will
switch and the output of each pin will be the unsynchro-
nized output of the comparator. The uncertainty of each
of the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 9-3 shows the comparator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4/T0CK1 pins while
in this mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
a ‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 9-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
CnINV
To RA3 or RA4/T0CK1 pin
To Data Bus
Q
D
Q1
EN
RD CMCON
Set CMIF bit
Q
D
Q3 * RD CMCON
EN
CL
From other Comparator
NRESET
DS40300B-page 60
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
