PIC16F62X
14.6.1 RB0/INT INTERRUPT
14.6.3 PORTB INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 14.9 for
details on SLEEP and Figure 14-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
14.6.4 COMPARATOR INTERRUPT
See Section 9.6 for complete description of comparator
interrupts.
14.6.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 14-17: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC
PC+1
PC+1
0005h
Instruction
Inst (PC+1)
—
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
fetched
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in ER oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS
Value on all
other resets(1)
Value on POR
Reset
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
INTCON
GIE
EEIF
EEIE
PEIE
CMIF
CMIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
—
T0IF
INTF
RBIF
0000 000x
0000 -000
0000 -000
0000 000u
0000 -000
0000 -000
0Ch
PIR1
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
—
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
DS40300B-page 108
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
