PIC16F62X
14.5.5 TIME-OUT SEQUENCE
14.5.6 POWER CONTROL (PCON)/
STATUS REGISTER
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in ER mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 14-10,
Figure 14-11 and Figure 14-12 depict time-out
sequences.
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOD = 0
indicating that a brown-out has occurred. The BOD
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-11). This is useful for testing purposes
or to synchronize more than one PIC16F62X device
operating in parallel.
Bit1 is POR (Power-on-reset). It is
a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (VDD may have
gone too low).
Table 14-6 shows the reset conditions for some special
registers, while Table 14-7 shows the reset conditions
for all the registers.
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up
Brown-out Reset
Oscillator Configuration
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
ER
72 ms + 1024 TOSC
72 ms
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
—
72 ms
—
TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOD
TO
PD
0
0
0
1
1
1
1
1
X
X
X
0
1
1
1
1
1
0
X
X
0
0
u
1
1
X
0
X
u
0
u
0
Power-on-reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Detect
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP
Legend: u = unchanged, x = unknown
TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Value on all
other resets(1)
Value on POR
Reset
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0001 1xxx
---- 1-0x
000q quuu
---- u-uq
03h
STATUS
PCON
RPO
TO
PD
Z
DC
C
IRP
RP1
8Eh
—
—
—
—
OSCF
—
POR
BOD
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
DS40300B-page 102
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
