PIC16F87XA
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
Bit 7
GIE
PSPIF
(1)
Bit 6
PEIE
ADIF
Bit 5
TMR0IE
RCIF
RCIE
Bit 4
INTE
TXIF
TXIE
Bit 3
RBIE
SSPIF
SSPIE
Bit 2
TMR0IF
CCP1IF
CCP1IE
Bit 1
INTF
TMR2IF
TMR2IE
Bit 0
RBIF
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
INTCON
10Bh, 18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
PIR1
PIE1
TMR1L
0000 000x 0000 000u
TMR1IF
0000 0000 0000 0000
TMR1IE
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PSPIE
(1)
ADIE
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu
x
= unknown,
u
= unchanged,
-
= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
DS39582A-page 58
Advance Information
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
