PIC16F87XA
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Details
on
page:
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
100h(3) INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 29, 148
101h
TMR0
Timer0 Module Register
xxxx xxxx 53, 148
0000 0000 28, 148
0001 1xxx 20, 148
xxxx xxxx 29, 148
102h(3) PCL
103h(3) STATUS
104h(3) FSR
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
105h
106h
107h
108h
109h
—
PORTB
—
—
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 43, 148
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
10Ah(1,3) PCLATH
10Bh(3) INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 28, 148
0000 000x 22, 148
xxxx xxxx 37, 149
xxxx xxxx 37, 149
--xx xxxx 37, 149
---- xxxx 37, 149
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
10Ch
10Dh
10Eh
10Fh
EEDATA
EEADR
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
EEDATH
EEADRH
—
—
—
—
EEPROM Data Register High Byte
(5)
—
—
EEPROM Address Register High Byte
Bank 3
180h(3) INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 29, 148
181h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
1111 1111 21, 148
0000 0000 28, 148
0001 1xxx 20, 148
xxxx xxxx 29, 148
182h(3) PCL
183h(3) STATUS
184h(3) FSR
PD
Z
Indirect Data Memory Address Pointer
Unimplemented
185h
186h
187h
188h
189h
—
—
—
TRISB
PORTB Data Direction Register
Unimplemented
1111 1111 43, 148
—
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
18Ah(1,3) PCLATH
18Bh(3) INTCON
—
—
PEIE
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 28, 148
0000 000x 22, 148
x--- x000 32, 149
---- ---- 37, 149
GIE
INTE
RBIE
TMR0IF
WREN
INTF
WR
RBIF
RD
18Ch
18Dh
18Eh
EECON1
EECON2
—
EEPGD
—
WRERR
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
0000 0000
0000 0000
—
—
18Fh
—
Reserved maintain clear
Legend:
x
= unknown,
u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 19
MICROCHIP [ MICROCHIP ]
