PIC16F87XA
7.1
Timer2 Prescaler and Postscaler
7.2
Output of TMR2
The prescaler and postscaler counters are cleared
when any of the following occurs:
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset, or BOR)
TMR2 is not cleared when T2CON is written.
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on: Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0Bh, 8Bh, INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
(1)
0Ch
8Ch
11h
12h
92h
PIR1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0000 0000 0000 0000
(1)
PIE1
TMR2
T2CON
PR2
Timer2 Module’s Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582A-page 60
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
