PIC16F87XA
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Details
on
page:
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h(3)
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 29, 148
81h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
1111 1111 21, 148
0000 0000 28, 148
0001 1xxx 20, 148
xxxx xxxx 29, 148
--11 1111 41, 148
1111 1111 43, 148
1111 1111 45, 148
1111 1111 46, 148
0000 -111 48, 148
---0 0000 28, 148
0000 000x 22, 148
82h(3)
83h(3)
84h(3)
85h
PCL
STATUS
FSR
PD
Z
TRISA
TRISB
TRISC
TRISD
TRISE
—
—
86h
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
87h
88h(4)
89h(4)
8Ah(1,3) PCLATH
8Bh(3)
8Ch
8Dh
8Eh
8Fh
90h
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
INTCON
PIE1
GIE
PSPIE(2)
—
PEIE
ADIE
CMIE
—
TMR0IE
RCIE
—
INTE
TXIE
EEIE
—
RBIE
SSPIE
BCLIE
—
TMR0IF
CCP1IE
—
INTF
RBIF
TMR2IE TMR1IE 0000 0000 23, 149
PIE2
—
CCP2IE -0-0 0--0 25, 149
PCON
—
—
—
—
POR
BOR
SEN
BF
---- --qq 27, 149
Unimplemented
Unimplemented
—
—
—
—
—
91h
SSPCON2
PR2
GCEN ACKSTAT ACKDT
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
ACKEN
RCEN
PEN
R/W
RSEN
UA
0000 0000 81, 149
1111 1111 60, 149
0000 0000 77, 149
0000 0000 77, 149
92h
93h
SSPADD
SSPSTAT
—
94h
SMP
CKE
D/A
P
S
95h
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
96h
—
97h
—
98h
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 109, 149
0000 0000 111, 149
99h
Baud Rate Generator Register
Unimplemented
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
—
—
—
—
—
Unimplemented
CMCON
CVRCON
ADRESL
ADCON1
C2OUT C1OUT
CVREN CVROE
C2INV
CVRR
C1INV
CIS
CM2
CM1
CM0
0000 0111 133, 149
000- 0000 139, 149
xxxx xxxx 131, 149
—
CVR3
CVR2
CVR1
CVR0
A/D Result Register Low Byte
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0 0---0000 126, 149
x
= unknown,
u
= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
DS39582A-page 18
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
