PIC16F87XA
FIGURE 17-17:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
Pin
121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
Standard(F)
SLAVE)
Clock high to data out valid
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Extended(LF)
121
122
†
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 17-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
125
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK↓ (DT hold time)
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 191
MICROCHIP [ MICROCHIP ]
