PIC16F87XA
The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
14.11 Interrupts
The PIC16F87XA family has up to 15 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 14-10:
INTERRUPT LOGIC
EEIF
EEIE
PSPIF(1)
PSPIE(1)
ADIF
ADIE
Wake-up (If in SLEEP mode)
TMR0IF
TMR0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
CMIF
CMIE
Note 1:
PSP interrupt is implemented only on PIC16F874A/877A devices.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 151