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PIC16F873A-I/SO 参数 Datasheet PDF下载

PIC16F873A-I/SO图片预览
型号: PIC16F873A-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
FIGURE 9-1:  
MSSP BLOCK DIAGRAM  
(SPI MODE)  
9.0  
9.1  
MASTER SYNCHRONOUS  
SERIAL PORT (MSSP)  
MODULE  
Internal  
Data Bus  
Read  
Write  
Master SSP (MSSP) Module  
Overview  
SSPBUF reg  
The Master Synchronous Serial Port (MSSP) module is  
a serial interface, useful for communicating with other  
peripheral or microcontroller devices. These peripheral  
devices may be serial EEPROMs, shift registers, dis-  
play drivers, A/D converters, etc. The MSSP module  
can operate in one of two modes:  
RC4/  
SDI/  
SDA  
SSPSR reg  
Shift  
Clock  
bit0  
RC5/SDO  
• Serial Peripheral Interface (SPI)  
• Inter-Integrated Circuit (I2C)  
- Full Master Mode  
Peripheral OE  
RA5/  
SS/  
AN4  
Control  
Enable  
SS  
- Slave mode (with general address call)  
The I2C interface supports the following modes in  
hardware:  
Edge  
Select  
• Master mode  
• Multi-Master mode  
• Slave mode  
2
Clock Select  
RC3/  
SCK/  
SCL/  
LVDIN  
SSPM3:SSPM0  
9.2  
Control Registers  
SMP:CKE  
2
4
TMR2 output  
2
(
)
The MSSP module has three associated registers.  
These include a status register (SSPSTAT) and two  
control registers (SSPCON and SSPCON2). The uses  
of these registers and their individual configuration bits  
differ significantly, depending on whether the MSSP  
module is operated in SPI or I2C mode.  
Edge  
Select  
TOSC  
Prescaler  
4, 16, 64  
Data to TX/RX in SSPSR  
TRIS bit  
Additional details are provided under the individual  
sections.  
Note: When the SPI is in Slave mode with SS pin  
control enabled (SSPCON<3:0> = 0100),  
the state of the SS pin can affect the state  
read back from the TRISC<5> bit. The  
Peripheral OE signal from the SSP module  
into PORTC, controls the state that is read  
back from the TRISC<5> bit (see  
Section 4.3 for information on PORTC). If  
Read-Modify-Write instructions, such as  
BSF,are performed on the TRISC register  
while the SS pin is high, this will cause the  
TRISC<5> bit to be set, thus disabling the  
SDO output.  
9.3  
SPI Mode  
The SPI mode allows 8 bits of data to be synchronously  
transmitted and received simultaneously. All four  
modes of SPI are supported. To accomplish communi-  
cation, typically three pins are used:  
• Serial Data Out (SDO) - RC5/SDO  
• Serial Data In (SDI) - RC4/SDI/SDA  
• Serial Clock (SCK) - RC3/SCK/SCL/LVDIN  
Additionally a fourth pin may be used when in a Slave  
mode of operation:  
• Slave Select (SS) - RA5/SS/AN4  
Figure 9-1 shows the block diagram of the MSSP  
module when operating in SPI mode.  
2001 Microchip Technology Inc.  
Advance Information  
DS39582A-page 69  
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