PIC16F87XA
Reset
STATUS Register
C Bit ........................................................................... 20
Brown-out Reset (BOR).
See Brown-out Reset (BOR).
Power-on Reset (POR).
See Power-on Reset (POR).
RESET Conditions for PCON Register ....................147
RESET Conditions for Program Counter .................147
RESET Conditions for STATUS Register ................147
WDT Reset. See Watchdog Timer (WDT)
DC Bit ........................................................................ 20
IRP Bit ........................................................................ 20
PD Bit ..................................................................20, 145
RP1:RP0 Bits ............................................................. 20
TO Bit ..................................................................20, 145
Z Bit ........................................................................... 20
Synchronous Master Reception
RESET, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer, and Brown-out
Associated Registers ............................................... 121
Synchronous Master Transmission
Reset Requirements ................................................182
Revision History ...............................................................207
Associated Registers ............................................... 120
Synchronous Serial Port Interrupt ...................................... 24
Synchronous Slave Reception
Associated Registers ............................................... 123
Synchronous Slave Transmission
S
Sales and Support ............................................................219
SCI. See USART
Associated Registers ............................................... 123
SCK ....................................................................................69
SDI .....................................................................................69
SDO ...................................................................................69
Serial Clock, SCK ...............................................................69
Serial Communication Interface. See USART.
Serial Data In, SDI .............................................................69
Serial Data Out, SDO .........................................................69
Serial Peripheral Interface. See SPI.
T
T1CKPS0 bit ...................................................................... 55
T1CKPS1 bit ...................................................................... 55
T1CON ............................................................................... 19
T1CON Register ...........................................................17, 19
T1OSCEN bit ..................................................................... 55
T1SYNC bit ........................................................................ 55
T2CKPS0 bit ...................................................................... 59
T2CKPS1 bit ...................................................................... 59
T2CON Register ...........................................................17, 19
TAD ................................................................................... 129
Time-out Sequence ......................................................... 146
Timer0 ................................................................................ 51
Associated Registers ................................................. 53
Clock Source Edge Select (T0SE Bit) ....................... 21
Clock Source Select (T0CS Bit) ................................. 21
External Clock ............................................................ 52
Interrupt ..................................................................... 51
Overflow Enable (TMR0IE Bit) ................................... 22
Overflow Flag (TMR0IF Bit) ................................22, 152
Overflow Interrupt .................................................... 152
Prescaler .................................................................... 52
T0CKI ......................................................................... 52
Timer0 and Timer1 External Clock
Requirements .......................................................... 183
Timer1 ...........................................................................55, 56
Associated Registers ................................................. 58
Asynchronous Counter Mode .................................... 57
Reading and Writing to ...................................... 57
Counter Operation ..................................................... 56
Operation in Timer Mode ........................................... 56
Oscillator .................................................................... 57
Capacitor Selection ............................................ 57
Prescaler .................................................................... 58
Resetting of Timer1 Registers ................................... 58
Resetting Timer1 using a CCP
Slave Select Synchronization .............................................75
Slave Select, SS ................................................................69
SLEEP .............................................................. 141, 145, 154
Software Simulator (MPLAB SIM) ....................................166
SPBRG Register ................................................................18
Special Features of the CPU ............................................141
Special Function Registers ................................................17
Special Function Registers (SFRs) ....................................17
Speed, Operating .................................................................1
SPI Mode ..................................................................... 69, 75
Associated Registers .................................................77
Bus Mode Compatibility .............................................77
Effects of a RESET ....................................................77
Enabling SPI I/O .........................................................73
Master Mode ..............................................................74
Master/Slave Connection ...........................................73
Serial Clock ................................................................69
Serial Data In .............................................................69
Serial Data Out ...........................................................69
Slave Select ...............................................................69
Slave Select Synchronization .....................................75
SLEEP Operation .......................................................77
SPI Clock ...................................................................74
Typical Connection .....................................................73
SPI Mode Requirements ..................................................188
SS ......................................................................................69
SSP
SPI Master/Slave Connection ....................................73
SSPADD Register ..............................................................18
SSPBUF .............................................................................19
SSPBUF Register ..............................................................17
SSPCON Register ..............................................................17
SSPCON2 Register ............................................................18
SSPIF .................................................................................24
SSPOV ...............................................................................99
SSPSTAT Register ............................................................18
R/W Bit ................................................................. 82, 83
Stack ..................................................................................28
Overflows ...................................................................28
Underflow ...................................................................28
Trigger Output ........................................... 57
Synchronized Counter Mode ..................................... 56
TMR1H ...................................................................... 57
TMR1L ....................................................................... 57
Timer2 ................................................................................ 59
Associated Registers ................................................. 60
Output ........................................................................ 60
Postscaler .................................................................. 59
Prescaler .................................................................... 59
Timijg Diagrams
SPI Master Mode (CKE = 1, SMP = 1) .................... 186
DS39582A-page 214
Advance Information
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
