PIC16F87XA
TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
Register
PIE1
Devices
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 974 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
73A 74A 76A 77A
r000 0000
0000 0000
-0-0 0--0
---- --qq
0000 0000
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
0000 0111
000- 0000
xxxx xxxx
00-- 0000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
---- ----
r000 0000
0000 0000
-0-0 0--0
---- --uu
0000 0000
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
0000 0111
000- 0000
uuuu uuuu
00-- 0000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u000
---- ----
ruuu uuuu
uuuu uuuu
-u-u u--u
---- --uu
uuuu uuuu
1111 1111
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uu-- uuuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- uuuu
---- ----
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
ADRESL
ADCON1
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for RESET value for specific condition.
FIGURE 14-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 149
MICROCHIP [ MICROCHIP ]
