PIC16F87XA
FIGURE 10-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
When setting up a Synchronous Slave Transmission,
follow these steps:
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
If two words are written to the TXREG and then the
7. Start transmission by loading data to the TXREG
register.
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
DS39582A-page 122
AdvanceInformation
2001 Microchip Technology Inc.