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PIC16F873A-I/SO 参数 Datasheet PDF下载

PIC16F873A-I/SO图片预览
型号: PIC16F873A-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
The STOP condition begins with SDA asserted low.  
When SDA is sampled low, the SCL pin is allowed to  
float. When the pin is sampled high (clock arbitration),  
the baud rate generator is loaded with SSPADD<6:0>  
and counts down to 0. After the BRG times out, SDA is  
sampled. If SDA is sampled low, a bus collision has  
occurred. This is due to another master attempting to  
drive a data ’0’ (Figure 9-31). If the SCL pin is sampled  
low before SDA is allowed to float high, a bus collision  
occurs. This is another case of another master attempt-  
ing to drive a data ’0’ (Figure 9-32).  
9.4.17.3  
Bus Collision During a STOP  
Condition  
Bus collision occurs during a STOP condition if:  
a) After the SDA pin has been de-asserted and  
allowed to float high, SDA is sampled low after  
the BRG has timed out.  
b) After the SCL pin is de-asserted, SCL is sam-  
pled low before SDA goes high.  
FIGURE 9-31:  
BUS COLLISION DURING A STOP CONDITION (CASE 1)  
SDA sampled  
TBRG  
TBRG  
TBRG  
low after TBRG,  
set BCLIF.  
SDA  
SDA asserted low  
SCL  
PEN  
BCLIF  
P
’0’  
’0’  
SSPIF  
FIGURE 9-32:  
BUS COLLISION DURING A STOP CONDITION (CASE 2)  
TBRG  
TBRG  
TBRG  
SDA  
SCL goes low before SDA goes high,  
set BCLIF.  
Assert SDA  
SCL  
PEN  
BCLIF  
P
’0’  
’0’  
SSPIF  
2001 Microchip Technology Inc.  
Advance Information  
DS39582A-page 107  
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