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PIC16F873A-I/SO 参数 Datasheet PDF下载

PIC16F873A-I/SO图片预览
型号: PIC16F873A-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
I2C MASTER MODE REPEATED  
START CONDITION TIMING  
Immediately following the SSPIF bit getting set, the  
user may write the SSPBUF with the 7-bit address in  
7-bit mode, or the default first address in 10-bit mode.  
After the first eight bits are transmitted and an ACK is  
received, the user may then transmit an additional eight  
bits of address (10-bit mode), or eight bits of data (7-bit  
mode).  
9.4.9  
A Repeated START condition occurs when the RSEN  
bit (SSPCON2<1>) is programmed high and the I2C  
logic module is in the IDLE state. When the RSEN bit is  
set, the SCL pin is asserted low. When the SCL pin is  
sampled low, the baud rate generator is loaded with the  
contents of SSPADD<5:0> and begins counting. The  
SDA pin is released (brought high) for one baud rate  
generator count (TBRG). When the baud rate generator  
times out, if SDA is sampled high, the SCL pin will be  
de-asserted (brought high). When SCL is sampled  
high, the baud rate generator is reloaded with the con-  
tents of SSPADD<6:0> and begins counting. SDA and  
SCL must be sampled high for one TBRG. This action is  
then followed by assertion of the SDA pin (SDA = 0) for  
9.4.9.1  
WCOL Status Flag  
If the user writes the SSPBUF when a Repeated  
START sequence is in progress, the WCOL is set and  
the contents of the buffer are unchanged (the write  
doesn’t occur).  
Note: Because queueing of events is not  
allowed, writing of the lower 5 bits of  
SSPCON2 is disabled until the Repeated  
START condition is complete.  
one TBRG while SCL is high. Following this, the RSEN  
,
bit (SSPCON2<1>) will be automatically cleared and  
the baud rate generator will not be reloaded, leaving  
the SDA pin held low. As soon as a START condition is  
detected on the SDA and SCL pins, the S bit  
(SSPSTAT<3>) will be set. The SSPIF bit will not be set  
until the baud rate generator has timed out.  
Note 1: If RSEN is programmed while any other  
event is in progress, it will not take effect.  
2: A bus collision during the Repeated  
START condition occurs if:  
• SDA is sampled low when SCL goes  
from low to high.  
• SCL goes low before SDA is  
asserted low. This may indicate that  
another master is attempting to  
transmit a data "1".  
FIGURE 9-20:  
REPEAT START CONDITION WAVEFORM  
Set S (SSPSTAT<3>)  
Write to SSPCON2  
occurs here.  
SDA = 1,  
SDA = 1,  
SCL = 1  
At completion of START bit,  
hardware clear RSEN bit  
and set SSPIF  
SCL (no change)  
TBRG  
TBRG  
TBRG  
1st Bit  
SDA  
Write to SSPBUF occurs here.  
TBRG  
Falling edge of ninth clock  
End of Xmit  
SCL  
TBRG  
Sr = Repeated START  
DS39582A-page 98  
AdvanceInformation  
2001 Microchip Technology Inc.  
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