PIC16F87XA
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the In-
Circuit Debugger and Low Voltage Programming func-
tion: RB3/PGM, RB6/PGC and RB7/PGD. The alter-
nate functions of these pins are described in the
Special Features Section.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
This interrupt-on-mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Strokes” (AN552).
FIGURE 4-4:
BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RB0/INT is discussed in detail in Section 14.11.1.
RBPU(2)
Weak
P
Pull-up
FIGURE 4-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
Data Bus
WR Port
D
Q
I/O
pin(1)
VDD
CK
TRIS Latch
RBPU(2)
Weak
P
Pull-up
D
Q
Data Latch
TTL
Data Bus
WR Port
Input
Buffer
D
Q
WR TRIS
CK
I/O
pin(1)
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
WR TRIS
RD TRIS
TTL
CK
Input
Buffer
ST
Buffer
EN
RB0/INT
RB3/PGM
Latch
Q
Q
D
Schmitt Trigger
Buffer
RD Port
RD Port
EN
Q1
Set RBIF
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
D
RD Port
Q3
From other
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
RB7:RB4 pins
EN
RB7:RB6
In Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS39582A-page 42
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
