PIC16F84A
2.2.2
SPECIAL FUNCTION REGISTERS
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
The Special Function Registers (Figure 2-1 and
Table 2-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
TABLE 2-1
REGISTER FILE SUMMARY
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Addr Name
Bank 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
01h
02h
INDF
TMR0
PCL
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
---- ----
xxxx xxxx
0000 0000
---- ----
uuuu uuuu
0000 0000
Low order 8 bits of the Program Counter (PC)
(2)
TO
Indirect data memory address pointer 0
03h
04h
STATUS
FSR
IRP
RP1
RP0
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x xxxx
000q quuu
uuuu uuuu
---u uuuu
(4)
—
—
—
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
05h
06h
PORTA
PORTB
(5)
RB7
RB6
RB5
RB0/INT xxxx xxxx
uuuu uuuu
07h
08h
09h
Unimplemented location, read as '0'
EEPROM data register
---- ----
xxxx xxxx
xxxx xxxx
---- ----
uuuu uuuu
uuuu uuuu
EEDATA
EEADR
EEPROM address register
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF
---0 0000
---0 0000
0000 000u
GIE
EEIE
T0IE
INTF
RBIF
0000 000x
Bank 1
80h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
---- ----
81h
82h
OPTION_REG RBPU INTEDG
T0CS
Low order 8 bits of Program Counter (PC)
IRP RP1 RP0 TO
Indirect data memory address pointer 0
PORTA data direction register
T0SE
PSA
PS2
PS1
DC
PS0
C
1111 1111
0000 0000
1111 1111
0000 0000
PCL
(2)
83h
84h
85h
86h
STATUS
FSR
PD
Z
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---- ----
000q quuu
uuuu uuuu
---1 1111
1111 1111
---- ----
TRISA
TRISB
—
—
—
PORTB data direction register
Unimplemented location, read as '0'
87h
88h
EECON1
EECON2
—
—
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---- ----
---0 q000
---- ----
89h
EEPROM control register 2 (not a physical register)
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF
---0 0000
0000 000x
---0 0000
0000 000u
GIE
EEIE
T0IE
INTF
RBIF
Legend: x= unknown, u= unchanged. -= unimplemented read as '0', q= value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
1998 Microchip Technology Inc.
Preliminary
DS35007A-page 7
MICROCHIP [ MICROCHIP ]
