PIC16F84A
FIGURE 3-1: BLOCK DIAGRAM OF PINS
RA3:RA0
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
bus
D
Q
Q
VDD
P
WR
Port
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
CK
Mid-Range
Reference
Manual,
Data Latch
3.1
PORTA and TRISA Registers
N
I/O pin
D
Q
Q
PORTA is a 5-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
WR
TRIS
VSS
CK
TRIS Latch
TTL
input
buffer
Note: On a Power-on Reset, these pins are con-
RD TRIS
figured as inputs and read as '0'.
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Q
D
EN
RD PORT
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Note: I/O pins have protection diodes to VDD and VSS.
EXAMPLE 3-1: INITIALIZING PORTA
BCF
STATUS, RP0
;
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0x0F
; Value used to
; initialize data
; direction
MOVWF TRISA
; Set RA<3:0> as inputs
; RA4 as output
; TRISA<7:5> are always
; read as '0'.
1998 Microchip Technology Inc.
Preliminary
DS35007A-page 13
MICROCHIP [ MICROCHIP ]
