PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
45, 96
26, 96
100h
101h
TMR0
PCL
Timer0 Module Register
xxxx xxxx
0000 0000
(4)
Program Counter (PC) Least Significant Byte
102h
(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
19, 96
103h
(4)
FSR
—
Indirect Data Memory Address Pointer
Unimplemented
xxxx xxxx
27, 96
—
104h
105h
106h
107h
108h
109h
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
34, 96
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE TMR0IF INTF RBIF
---0 0000
21, 96
10Ah
(4)
INTCON
PMDATA
PMADR
GIE
PEIE
TMR0IE
0000 000x
23, 96
10Bh
10Ch
10Dh
10Eh
10Fh
Data Register Low Byte
Address Register Low Byte
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
29, 97
29, 97
29, 97
PMDATH
PMADRH
—
—
—
—
Data Register High Byte
Address Register High Byte
—
29, 97
Bank 3
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
180h
181h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 20, 44, 96
(4)
PCL
0000 0000
0001 1xxx
xxxx xxxx
26, 96
19, 96
27, 96
182h
(4)
STATUS
PD
Z
DC
C
183h
(4)
FSR
—
Indirect Data Memory Address Pointer
Unimplemented
184h
185h
186h
187h
188h
189h
—
—
34, 96
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111
—
—
—
—
Unimplemented
—
—
Unimplemented
—
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
PEIE
—
—
TMR0IE
—
---0 0000
0000 000x
21, 96
23, 96
29, 97
18Ah
(4)
INTCON
GIE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
18Bh
(6)
18Ch
18Dh
18Eh
18Fh
PMCON1
—
—
—
—
1--- ---0
—
—
—
—
—
Unimplemented
Reserved maintain clear
Reserved maintain clear
0000 0000
0000 0000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 18
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
