PIC16F7X
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition period must pass
before the conversion can be started.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023). In general, however, given a max-
imum source impedance of 10 kΩ and at a temperature
of 100°C, TACQ will be no more than 16 µsec.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
= DAC Capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
= leakage current at the pin due to
various junctions
I leakage
2V
= interconnect resistance
= sampling switch
RIC
SS
5 6 7 8 9 10 11
Sampling Switch
= sample/hold capacitance (from DAC)
CHOLD
(kΩ)
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
DS30325B-page 86
2002 Microchip Technology Inc.