PIC16F7X
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating
RESET condition.
a device
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit, WDTE (Section 12.1).
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
M
1
U
WDT Timer
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
PWRTE(1) WDTE
PSA PS2
Bit 2
Bit 1
Bit 0
2007h
Config. bits
BODEN(1)
INTEDG
—
CP0
FOSC1
PS1
FOSC0
PS0
81h,181h
OPTION_REG RBPU
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
2002 Microchip Technology Inc.
DS30325B-page 101