PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
300h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
301h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
302h(2)
303h(2)
304h(2)
305h(2)
306h(2)
307h(2)
308h(2)
309h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
1111 1111 1111 1111
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
30Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
30Bh(2)
30Ch
30Dh
30Eh
30Fh
310h
311h
INTCON
TRISF
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTF Data Direction Register
TRISG
—
—
—
TRISG5
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0 --11 1111 --11 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
Legend:
P3M<1:0>
P3RSEN
DC3B<1:0>
CCP3M<1:0>
0000 0000 0000 0000
P3DC<6:0>
0000 0000 0000 0000
CCP3ASE
—
CCP3AS<2:0>
STR3SYNC
PSS3AC<1:0>
PSS3BD<1:0>
0000 0000 0000 0000
—
—
STR3D
STR3C
STR3B
STR3A ---0 0001 ---0 0001
Unimplemented
—
—
CCPR4L
CCPR4H
CCP4CON
—
Capture/Compare/PWM Register 4 (LSB)
Capture/Compare/PWM Register 4 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC4B<1:0>
CCP4M<3:0>
Unimplemented
—
—
CCPR5L
CCPR5H
CCP5CON
—
Capture/Compare/PWM Register 5 (LSB)
Capture/Compare/PWM Register 5 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC5B<1:0>
CCP5M<3:0>
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 37
MICROCHIP [ MICROCHIP ]
