PIC16F/LF1946/47
TABLE 23-2: I2C BUS TERMS
23.4.5 START CONDITION
The I2C specification defines a Start condition as a
transition of SDAx from a high to a low state while
SCLx line is high. A Start condition is always gener-
ated by the master and signifies the transition of the
bus from an Idle to an Active state. Figure 23-10
shows wave forms for Start and Stop conditions.
TERM
Description
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
A bus collision can occur on a Start condition if the
module samples the SDAx line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
Slave
The device addressed by the mas-
ter.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
23.4.6 STOP CONDITION
A Stop condition is a transition of the SDAx line from
low-to-high state while the SCLx line is high.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Note: At least one SCLx low time must appear
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDAx and SCLx lines are
high.
23.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
Clock Stretching When a device on the bus holds
SCLx low to stall communication.
23.4.8 START/STOP CONDITION INTERRUPT
MASKING
Bus Collision
Any time the SDAx line is sampled
low by the module while it is out-
putting and expected high state.
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
DS41414A-page 248
Preliminary
2010 Microchip Technology Inc.
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