PIC16C63A/65B/73B/74B
13.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 13-6:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 MUX (Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 13-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
BODEN(1)
INTEDG
PWRTE(1)
PSA
Config. bits
–
CP1
CP0
OPTION_REG RBPU
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS30605C-page 96
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
