PIC16C63A/65B/73B/74B
FIGURE 5-6:
PORTD BLOCK DIAGRAM
5.4
PORTD and TRISD Registers
Data
Bus
Note: The PIC16C63A and PIC16C73B do not
provide PORTD. The PORTD and TRISD
registers are not implemented.
D
Q
(1)
WR
Port
I/O pin
CK
Data Latch
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
D
Q
WR
TRIS
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
PORTD FUNCTIONS
Name
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
ST/TTL
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
TRISD PORTD Data Direction register
TRISE IBF OBF IBOV PSPMODE
—
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS30605C-page 34
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
