PIC16C63A/65B/73B/74B
FIGURE 16-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
71A
72
TscH
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
40
1.25TCY + 30
40
ns (Note 1)
TscL
ns
SCK input low time
(Slave mode)
72A
73
ns (Note 1)
TdiV2scH,
TdiV2scL
100
ns
Setup time of SDI data input to SCK edge
73A
74
TB2B
1.5TCY + 40
100
—
—
—
—
ns (Note 1)
Last clock edge of Byte1 to the 1st clock
edge of Byte2
TscH2diL,
TscL2diL
ns
Hold time of SDI data input to SCK edge
75
TdoR
—
—
—
—
—
—
—
—
10
20
10
10
20
10
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
SDO data output rise time PIC16CXX
PIC16LCXX
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC16CXX
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
TscH2doV,
TscL2doV
SDO data output valid
after SCK edge
PIC16CXX
PIC16LCXX
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605C-page 130
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
