欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16C73B-20/SP 参数 Datasheet PDF下载

PIC16C73B-20/SP图片预览
型号: PIC16C73B-20/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS微控制器 [28/40-Pin 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 184 页 / 2122 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16C73B-20/SP的Datasheet PDF文件第78页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第79页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第80页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第81页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第83页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第84页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第85页浏览型号PIC16C73B-20/SP的Datasheet PDF文件第86页  
PIC16C63A/65B/73B/74B  
The maximum recommended impedance for ana-  
log sources is 10 k. After the analog input channel is  
selected (changed), the acquisition time (TACQ) must  
pass before the conversion can be started.  
12.1 A/D Acquisition Requirements  
For the A/D converter to meet its specified accuracy,  
the charge holding capacitor (CHOLD) must be allowed  
to fully charge to the input channel voltage level. The  
analog input model is shown in Figure 12-2. The  
source impedance (RS) and the internal sampling  
switch (RSS) impedance directly affect the time  
required to charge the capacitor CHOLD. The sampling  
switch (RSS) impedance varies over the device voltage  
(VDD), Figure 12-2. The source impedance affects the  
offset voltage at the analog input (due to pin leakage  
current).  
To calculate the minimum acquisition time,  
Equation 12-1 may be used. This equation assumes  
that 1/2 LSb error is used (512 steps for the A/D). The  
1/2 LSb error is the maximum error allowed for the A/D  
to meet its specified resolution.  
For more information, see the PICmicroMid-Range  
MCU Family Reference Manual (DS33023). In general,  
however, given a maximum source impedance of  
10 kand a worst case temperature of 100°C, TACQ  
will be no more than 16 µsec.  
FIGURE 12-2:  
ANALOG INPUT MODEL  
VDD  
Sampling  
Switch  
VT = 0.6 V  
ANx  
SS  
RIC £ 1k  
RSS  
Rs  
CHOLD  
= DAC capacitance  
= 51.2 pF  
CPIN  
5 pF  
VA  
I leakage  
± 500 nA  
VT = 0.6 V  
VSS  
Legend: CPIN  
VT  
= input capacitance  
= threshold voltage  
6V  
5V  
VDD 4V  
3V  
I leakage = leakage current at the pin due to  
various junctions  
2V  
RIC  
= interconnect resistance  
= sampling switch  
SS  
5 6 7 8 9 10 11  
Sampling Switch  
CHOLD  
= sample/hold capacitance (from DAC)  
(k)  
EQUATION 12-1: ACQUISITION TIME  
TACQ  
=
Amplifier Settling Time +  
Hold Capacitor Charging Time +  
Temperature Coefficient  
=
TAMP + TC + TCOFF  
TAMP = 5 µS  
TC = - (51.2 pF)(1 k+ RSS + RS) In(1/511)  
TCOFF = (Temp -25°C)(0.05 µS/°C)  
DS30605C-page 82  
2000 Microchip Technology Inc.  
 复制成功!