PIC16C63A/65B/73B/74B
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.3
Timer1 Operation in
Asynchronous Counter Mode
Osc Type
Freq
C1
C2
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.1).
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In Asynchronous Counter mode, Timer1 can not be
used as a time-base for capture or compare opera-
tions.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
7.3.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
7.5
Resetting Timer1 using a CCP
Trigger Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
a
Timer1.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Exam-
ples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
7.4
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset or a
Brown-out Reset, which shuts off the timer and leaves a
1:1 prescale. In all other resets, the register is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
2000 Microchip Technology Inc.
DS30605C-page 45
MICROCHIP [ MICROCHIP ]
