PIC16C63A/65B/73B/74B
TABLE C-2:
Param
SPECIFICATION DIFFERENCES
PIC16C63/65A/73A/74A
PIC16C63A/65B/73B/74B
Symbol
Characteristic
Unit
No.
Min
Typ†
Max
Min
Typ†
Max
Core
D001
D001A
VDD
Supply Voltage
4.0
—
—
—
6.0
—
4.0
—
—
5.5
5.5
V
V
(1)
VBOR
3.65
-
D005
BVDD
VOD
Brown-out Reset Voltage
3.7
4.0
4.3
—
—
4.35
8.5
V
V
D150*
Open-Drain High Voltage on
RA4
—
—
14.0
A/D Converter
A20
131
VREF
TCNV
Reference voltage
3.0
—
VDD + 0.3
2.5
—
—
VDD + 0.3
V
Conversion time (Note 2)
—
9.5
—
11
11
TAD
(not including S/H time)
(Note 3)
(Note 4)
(Note 4)
SSP in SPI mode
71
TscH
SCK input high
time (Slave mode)
Continuous TCY+20
Single Byte
—
—
—
—
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
ns
ns
ns
71A
72
40
1.25TCY + 30
40
TscL
SCK input low
time
(Slave mode)
Continuous TCY+20
Single Byte
72A
73
TdiV2scH Setup time of SDI data input to
TdiV2scL SCK edge
50
—
50
—
—
—
—
10
—
—
—
25
100
1.5TCY + 40
100
—
—
—
—
—
—
ns
ns
ns
73A
(Note 5)
TB2B
Last clock edge of Byte1 to the
1st clock edge of Byte2
74
75
TscH2diL Hold time of SDI data input to
TscL2diL SCK edge
TdoR
SDO data output PIC16CXX
—
—
—
—
10
20
10
20
25
45
25
45
ns
ns
ns
ns
rise time
PIC16LCXX
PIC16CXX
PIC16LCXX
78
80
83
TscR
SCK output rise
time (Master
mode)
—
—
—
10
—
—
25
50
50
TscH2doV SDO data output PIC16CXX
—
—
—
—
50
ns
ns
TscL2doV valid after SCK
edge
PIC16LCXX
100
TscH2ssH SS ↑ after SCK edge
1.5TCY + 40
—
—
ns
TscL2ssH
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When BOR is enabled, the device will operate until VDD drops below VBOR.
2: ADRES register may be read on the following TCY cycle.
3: This is the time that the actual conversion requires.
4: This is the time from when the GO/DONE bit is set, to when the conversion result appears in ADRES.
5: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 167
MICROCHIP [ MICROCHIP ]
