PIC16C62B/72A
13.2
DC Characteristics: PIC16LC62B/72A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param Sym
Characteristic
Min Typ† Max Units
Conditions
No.
D001
D002*
D003
VDD
VDR
Supply Voltage
2.5
VBOR*
-
-
5.5
5.5
V
V
LP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
RAM Data Retention
Voltage (Note 1)
-
-
1.5
-
V
VPOR VDD Start Voltage to
ensure internal
VSS
-
V
See section on Power-on Reset for details
Power-on Reset signal
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
0.05
TBD
-
-
-
-
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
Power-on Reset signal
See section on Power-on Reset for details
D005
D010
VBOR Brown-out Reset
voltage trip point
3.65
-
-
4.35
3.8
V
BODEN bit set
IDD
Supply Current
2.0
mA XT, RC osc modes
(Note 2, 5)
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
-
22.5
48
µA LP OSC MODE
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
IPD
Power-down Current
(Note 3, 5)
-
-
-
7.5
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
Module Differential
Current (Note 6)
D022*
∆IWDT Watchdog Timer
-
-
6.0
TBD 200
20
µA WDTE BIT SET, VDD = 4.0V
µA BODEN bit set, VDD = 5.0V
D022A* ∆IBOR Brown-out Reset
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will
perform a brown-out reset when VDD falls below VBOR.
1998 Microchip Technology Inc.
Preliminary
DS35008B-page 85
MICROCHIP [ MICROCHIP ]
